1. Field of the Invention
The present invention relates in general to a process for fabricating semiconductor devices. In particular, the present invention relates to a process for fabricating semiconductor read-only memory cells by employing a polysilicon double-layer configuration for word lines.
2. Description of Related Art
As the technology of semiconductor fabrication advances, the integration density of memory cells of read-only memory (ROM) devices is increasing. More and more memory cells are squeezed into the same semiconductor die surface. The memory cell configuration of ROM devices have evolved several generations, beginning with the traditional two-state memory cells through the x-cell configuration, to the flat cell and modified flat cell configurations.
Conventional ROM device memory cells use channel transistors as the electric charge storage components, which are selectively implanted with impurities into the designated channel regions in the process of data programming. The purpose of this selective impurity implantation is to change the threshold voltage of those "programmed" memory cells, so that the memory cell transistor may be controlled in either the ON or OFF state to represent the binary bits one and zero respectively, or zero and one respectively depending on the memory cell supporting logic design.
A brief examination of the specifics of a conventional ROM device helps to explain the present invention. FIG. 1 (PRIOR ART) of the accompanying drawing shows the top view of a conventional ROM device which exhibits the configuration of several memory cells as observed from above. A cross-sectional view of the conventional ROM device memory cells taken along the II--II line is shown in FIG. 2 (PRIOR ART) and provides the details of the cells in another perspective.
As is shown in the drawing, a number of memory cells of the conventional ROM device are fabricated on a silicon substrate 10 of, for example, P-type. N.sup.+ source/drain regions (which become bit lines 14) are formed in the designated locations of the silicon substrate 10. The top view of FIG. 1 (PRIOR ART) clearly shows that the N.sup.+ source/drain regions (which become bit lines 14) are formed as long strips extending in one direction, namely, the vertical direction in the drawing which serve as the bit lines for the memory cells of the ROM device. A gate oxide layer 12 is then formed over the surface of the silicon substrate 10, and on top of which, gate electrodes (which become word lines 16) are formed to constitute the word lines for the memory cells in the ROM device. The word lines 16 are, as is shown in the top view of FIG. 1 (PRIOR ART), also formed as long strips that extend in the direction substantially orthogonal to the extending direction of the bit lines 14. In this example, the word lines 16 extend in the horizontal direction in FIG. 1 (PRIOR ART). Channel regions 18 for the memory cell transistors are formed between every two consecutive bit lines 14 and under each word line 16. The status of either conducting or blocking of each of the memory cell transistors determines its memory content as either binary one or zero (or either zero or one) respectively.
A ROM device having the basic memory cells as described above has all the memory cell transistors turned on, or, in other words, in their conducting state unless they have been programmed with data. To turn off a selected memory cell transistor, its channel region 18 would have to be implanted with P-type impurities. The process of programming the data bits into the selected memory cells of the ROM device is a process referred to as code implantation. Those memory cell transistors with their channel regions implanted with P-type impurities will have increased threshold voltage in the channel region.
However, such ROM devices having the memory cell configuration as described above have at least two disadvantages. Due to the need to reduce the size of virtually every dimension in the device as the ROM is increasingly miniaturized, it is inevitable that the width of the word lines for the memory cells is also reduced. Reduced-width word lines 16 represent increased electrical resistance over the cross section; and, increased electrical resistance directly translates into reduced memory access speed. Code implantation is a relatively inaccurate procedure considering that the dimensions of the memory cell transistor are reduced. Excessive diffusion of the implants in the designated channel region, as well as implantation location shifting constitute the primary problems of these conventional ROM devices. The typical operating characteristics exhibited by such faulty memory cells include typical electric current leakage, or a reduction of the breakdown voltage.